ASM International (Belgium)

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Title DOI
https://doi.org/10.1016/j.mee.2006.10.017 Study of silicide contacts to SiGe source/drain
https://doi.org/10.1109/ted.2007.914843 Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions
https://doi.org/10.1109/led.2008.919780 Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel
https://doi.org/10.2340/00015555-0494 Efficacy of a Single Oral Dose of 200 mg Pramiconazole in Vulvovaginal Yeast Infections: An Exploratory Phase IIa Trial
https://doi.org/10.1016/j.tsf.2008.08.139 Low temperature epitaxy and the importance of moisture control
https://doi.org/10.1016/j.mssp.2008.09.013 Stress analysis of Si1−xGex embedded source/drain junctions
https://doi.org/10.1109/vlsit.2002.1015448 Thermal stability and scalability of Zr-aluminate-based high-k gate stacks
https://doi.org/10.1109/essder.2004.1356543 Reliability of embedded SONOS memories
https://doi.org/10.1557/proc-487-411 New Generations of Position Sensitive Silicon Detectors
https://doi.org/10.1557/proc-765-d2.6 High-k Materials for Advanced Gate Stack Dielectrics: a Comparison of ALCVD and MOCVD as Deposition Technologies
https://doi.org/10.1149/1.2356267 3D Pattern Effects in RTA Radiative vs Conductive Heating
https://doi.org/10.1109/irps.2009.5173297 Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects
https://doi.org/10.1149/1.2209332 LEIS Study of ALD WN<em>x</em>C<em>y</em> Growth on Dielectric Layers
https://doi.org/10.1557/proc-745-n5.11 ALD HfO2 surface preparation study
https://doi.org/10.1016/j.mee.2009.06.019 Electrical demonstration of thermally stable Ni silicides on Si1−xCx epitaxial layers
https://doi.org/10.1016/j.apsusc.2008.02.138 Leakage current study of Si1−xCx embedded source/drain junctions
https://doi.org/10.1557/proc-745-n5.3 Physical-Chemical Evolution upon Thermal Treatments of Al2O3, HfO2 and Al/Hf Composite Materials Deposited by ALCVD™
https://doi.org/10.1016/j.tsf.2009.10.071 Stability of silicon germanium stressors
https://doi.org/10.1109/issm.2001.962998 Gate stack preparation with high-k materials in a cluster tool
https://doi.org/10.1149/1.2779086 Atomic Layer Deposition of Hafnium Based Gate Dielectric Layers for CMOS Applications
https://doi.org/10.1149/1.2779084 ALD La-Based Oxides for Vt-Tuning in High-K/Metal Gate Stacks
https://doi.org/10.23919/vlsit.2017.7998192 First demonstration of ∼3500 cm2/V-s electron mobility and sufficient BTI reliability (max V<inf>ov</inf> up to 0.6V) In<inf>0.53</inf>Ga<inf>0.47</inf>As nFET using an IL/LaSiO<inf>x</inf>/HfO<inf>2</inf> gate stack
https://doi.org/10.1109/iwgi.2003.159172 Implementation of high-k gate dielectrics - a status update
https://doi.org/10.1109/rtp.2007.4383834 Thermal Stability of Pt and C-Doped NiSi Films
https://doi.org/10.1149/ma2012-02/31/2598 Current Status of High-k and Metal Gates in CMOS
https://doi.org/10.1149/1.2721474 Radical-Assisted Silcore(R)CVD of Si3N4 and SiO2 Nanolaminates
https://doi.org/10.1149/1.3205061 Extreme Scaled Gate Dielectrics By Using ALD HfO2/SrTiO3 Composite Structures
https://doi.org/10.1109/ted.2017.2693211 The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping
https://doi.org/10.1007/978-3-030-44041-1_61 A Flexible and Interpretable Framework for Predicting Anomalous Behavior in Industry 4.0 Environments
https://doi.org/10.1149/ma2020-02241734mtgabs Investigation of Low Temperature SiP Epitaxy on 300 mm Si Substrate
https://doi.org/10.1149/ma2007-02/17/997 ALD La-Based Oxides for Vt-Tuning in High-K/Metal Gate Stacks
https://doi.org/10.1149/ma2008-02/24/1890 Batch Atomic Layer Deposition of HfO2 and ZrO2 Films Using Cyclopentadienyl Precursors
https://doi.org/10.4028/www.scientific.net/ssp.219.20 HF-Last Wet Clean in Combination with a Low Temperature GeH<sub>4</sub>-Assisted HCl <i>In Situ</i> Clean Prior to Si<sub>0.8</sub>Ge<sub>0.2</sub>-on-Si Epitaxial Growth
https://doi.org/10.1109/imw.2013.6582123 Vertical polysilicon Pinch-Off FET for 3D memory technology: Feasibility and electrical performance
https://doi.org/10.1117/12.837495 Litho scenario solutions for FinFET SRAM 22nm node
https://doi.org/10.4028/www.scientific.net/ssp.219.16 Catalyst Assisted Low Temperature Pre Epitaxial Cleaning for Si and SiGe Surfaces
https://doi.org/10.1143/jjap.49.05fd03 Integration of Porogen-Based Low-k Films: Influence of Capping Layer Thickness and Long Thermal Anneals on Low-k Damage and Reliability
https://doi.org/10.1149/1.2209299 Evaluation of Nb(Si)N as Metal Gate Material
https://doi.org/10.25046/aj030506 On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials
https://doi.org/10.1117/12.2536943 Large area EUV via yield analysis for single damascene process: voltage contrast, CD and defect metrology (Conference Presentation)
https://doi.org/10.1117/12.2585681 Oxides based resistive switching memories
https://doi.org/10.1149/ma2007-02/20/1119 Impact of Hf-Precursor Choice on Scaling and Performance of High-K Gate Dielectrics
https://doi.org/10.7567/jjap.51.05ec04 Impact of Hydrocarbon Control in Ultraviolet-Assisted Restoration Process for Extremely Porous Plasma Enhanced Chemical Vapor Deposition SiOCH Films withk= 2.0
https://doi.org/10.1149/ma2016-02/30/2003 (Invited) Selective Epitaxial Growth of High-P Si:P for Source/Drain Formation in Advanced Si nFETs
https://doi.org/10.1117/12.2642867 Curvilinear EUV mask: development of innovative mask metrology
https://doi.org/10.1117/12.2661307 Evaluation of TiN hardmask films to prevent line wiggling due to plasma-induced film stress
https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631469 First Demonstration of Superconducting Nb Contact on Heavily-Doped Group IV Semiconductor
https://doi.org/10.1117/12.3035360 Benefits of using advanced sub-resolution features for 0.55NA brightfield imaging
https://doi.org/10.1117/12.474610 157-nm technology: Where are we today?
https://doi.org/10.1109/rtp.2007.4383832 Pattern-Dependent Heating of 3D Structures
https://doi.org/10.1016/j.microrel.2004.11.048 Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey
https://doi.org/10.1063/1.2177375 Exoelectron emission from silicon nanocrystals
https://doi.org/10.1063/1.2401490 Simplifying the 45nm SDE Process with ClusterBoron® and ClusterCarbon™ Implantation
https://doi.org/10.1149/1.2778649 Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions
https://doi.org/10.1557/proc-0917-e11-04 Highly Scalable ALD-deposited Hafnium Silicate Gate Stacks for Low Standby Power Applications
https://doi.org/10.1557/proc-745-n2.3 Effect of Al-content and Post Deposition Annealing on the Electrical Properties of Ultra-thin HfAlxOy Layers
https://doi.org/10.1117/12.608499 <title>SIGEM, low-temperature deposition of poly-SiGe MEMs structures on standard CMOS circuits (Invited Paper)</title>
https://doi.org/10.1117/12.474250 Progress in 157-nm resist performance and potential
https://doi.org/10.1109/iitc.2006.1648641 Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node
https://doi.org/10.1002/pssc.200881457 Influence of the strain‐relaxation induced defect creation on the leakage current of embedded Si1–xGex source/drain junctions
https://doi.org/10.1016/j.mee.2009.06.036 Variation in process conditions of porogen-based low-k films: A method to improve performance without changing existing process steps in a sub-100nm Cu damascene integration route
https://doi.org/10.1109/iwjt.2007.4279969 Emissivity independent heating of 3D patterns
https://doi.org/10.1557/proc-830-d6.1 Improved size dispersion of silicon nanocrystals grown in a batch LPCVD reactor
https://doi.org/10.1109/essder.2004.1356494 Work function stability of thermal ALD Ta(Si)N gate electrodes on HfO/sub 2/ [CMOS device applications]
https://doi.org/10.1109/iitc.2002.1014956 Deposition of Cu barrier and seed layers with atomic layer control
https://doi.org/10.1117/12.436849 Process optimization for sub-100-nm gate patterns using phase edge lithography
https://doi.org/10.1587/transele.e96.c.699 Nonvolatile Polymer Memory-Cell Embedded with Ni Nanocrystals Surrounded by NiO in Polystyrene
https://doi.org/10.1149/1.3203956 On the Low-frequency Noise Performance of Embedded Si:C nMOSFETs
https://doi.org/10.4028/www.scientific.net/ssp.131-133.95 Influence of the Highly-Doped Drain Implantation and the Window Size on Defect Creation in p<sup>+</sup>/n Si<sub>1-X</sub>Ge<sub>x</sub> Source/Drain Junctions
https://doi.org/10.1149/1.3360696 On the Process and Material Sensitivities for High-k Based Dielectrics
https://doi.org/10.1149/ma2006-02/20/1018 Low Temperature Silcore a-Silicon Deposition
https://doi.org/10.1557/proc-765-d2.10 Physical-Chemical Evolution of Hf-aluminates upon Thermal Treatments
https://doi.org/10.1149/06907.0119ecst (Invited) ALD Materials for the Integration of III-V Based Transistors
https://doi.org/10.1149/1.3205059 Atomic Layer Deposition of GdHfOx Thin Films
https://doi.org/10.1149/1.2779585 A Morphological, Chemical and Electrical Study of HfSiON Films for Inter Poly Dielectric Applications in Flash Memories
https://doi.org/10.1149/ma2005-02/12/463 LEIS Study of ALD WNxCy on Dielectric Layers
https://doi.org/10.1149/ma2008-02/24/1915 Atomic Layer Deposition of Hf-based Materials in Semiconductor Applications
https://doi.org/10.1149/ma2009-02/23/2035 Atomic Layer Deposition of GdAlOx and GdHfOx Using Gd(iPr-Cp)3
https://doi.org/10.7567/ssdm.2014.e-1-2 Combined PEALD Gate-Dielectric and In-Situ SiN Cap-Layer for Reduced V<sub>th</sub> Shift and R<sub>DS-ON</sub> Dispersion of AlGaN/GaN HEMTs on 200 mm Si Wafer
https://doi.org/10.1149/ma2010-02/22/1523 LaHfOx Films Analyses for NVM Applications
https://doi.org/10.1117/12.2258040 Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist
https://doi.org/10.1149/ma2009-02/23/2037 Extreme Scaled Gate Dielectrics by using ALD Hf-based Composite Materials
https://doi.org/10.1109/ulis.2017.7962599 Feasibility demonstration of new e-NVM cells suitable for integration at 28nm
https://doi.org/10.1117/12.2281623 EUV exposure tool stability at IMEC (Conference Presentation)
https://doi.org/10.1016/j.resuscitation.2019.12.034 Reply to Chest-compression-only after drowning: A call for more research
https://doi.org/10.1149/ma2020-02241732mtgabs B and Ga Co-Doping in Epitaxial SiGe: Challenges and Opportunities
https://doi.org/10.1117/12.2584807 Electrical validation of massive E-beam defect metrology in EUV-patterned interconnects
https://doi.org/10.1117/12.2583870 NXE:3400 OPC process monitoring: model validity vs process variability
https://doi.org/10.1109/istdm.2006.246508 Highly Tensile Strained Silicon Carbon Phosphorus Alloys Epitaxially Grown into Recessed Source Drain Areas of NMOS devices
https://doi.org/10.7567/ssdm.2019.h-1-04 Improvement of HRS Variability in OxRRAM by Tailored Metallic Liner
Ultra-low Specific Contact Resistivity (3.2×10 -10 Ω-cm 2 ) of Ti/Si 0.5 Ge 0.5 Contact: Deep Insights into the Role of Interface Reaction and Ga Co-doping
https://doi.org/10.1117/12.2600937 28nm-pitch Ru interconnects patterned with a 0.33NA-EUV single exposure
https://doi.org/10.1117/12.2601587 Contour-based variability decomposition for stochastic band metrology
https://doi.org/10.1117/12.2600938 iN5 EUV single expose patterning evaluation for via layers
https://doi.org/10.1149/osf.io/3fvqn #AiMES2018_20181002_1400_Low-T-SiGe_Porret
https://doi.org/10.1149/ma2007-02/20/1160 A Morphological, Chemical and Electrical Study of HfSiON Films Properties for Interpoly Dielectric Applications in Flash Memories
https://doi.org/10.1149/ma2006-02/20/1005 3D Pattern Effects in RTA Radiative vs Conductive Heating
https://doi.org/10.1149/ma2007-02/19/1097 Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions
https://doi.org/10.1149/ma2014-02/35/1855 Characterization of Epitaxial Si:C:P and Si:P Layers for Source/Drain Formation in Advanced Bulk FinFETs
https://doi.org/10.1149/ma2007-02/17/999 Atomic Layer Deposition of Hafnium Based Gate Dielectric Layers for CMOS Applications